Marvell Engineer, Senior Logic Design in Santa Clara, California
Successful candidates must demonstrate some of the following qualifications:
BS/MS in EE/CS required
Knowledge of CPU architecture; understanding of Verilog, simulator, debug
Experience with assembly/C/C /Perl
In-depth knowledge of advanced verification flow (constrained random, assertion, functional coverage, code coverage)
Familiarity with SystemVerilog/UVM/formal verification/emulation is a plus
BS w/ 2 year of logic front-end design experience.
4 years experience preferredor MS in electrical engineering, computer science or equivalent.
Job: *Engineering - Hardware
Title: Engineer, Senior Logic Design
Location: California-Santa Clara
Requisition ID: 15-16117